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A modular architecture for a 6.4-Gbyte/s, 8-Mbit media chip

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9 Author(s)
Watanabe, T. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Fujita, R. ; Yanagisawa, K. ; Tanaka, H.
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Develops a modular architecture for a DRAM-integrated, multimedia chip, or media chip with a data transfer rate of 6 to 12 Gbyte/s. The DRAM macro enables the design flexibility both for DRAM capacity and the logic-memory interface to meet a wide variety of applications. A 6.4-Gbyte/s. 8-Mbit test chip was fabricated.

Published in:

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Date of Conference:

13-15 June 1996