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Self resetting logic register and incrementer

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5 Author(s)
R. A. Haring ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; M. S. Milshtein ; T. I. Chappell ; S. H. Dhong
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Register circuitry is described which is suitable for use with Self Resetting CMOS (SRCMOS) logic. It is level sensitive scan design (LSSD) compatible and complies with and implements the SRCMOS test modes. The register has been coupled to a novel high performance self resetting incrementer, which is based on a carry lookahead tree implemented in negative logic, and with a strobed final sum circuit. Hardware measurements are presented, showing a 900 ps 58-bit incrementer delay.

Published in:

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Date of Conference:

13-15 June 1996