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The data holding circuits which use an Intermittent Power Supply (IPS) scheme are proposed for sub-1V Multiple Threshold (MT) CMOS technology. This scheme can use low V/sub T/ transistors without any increase of leakage currents. As a result, no extra data holding circuit and no degradation of operating speed will be achieved. An experimental latch circuit has been fabricated in 0.35 /spl mu/m MT-CMOS technology and 30% smaller area, 10% shorter delay time, and 10% lower active power consumption compared with a conventional MT-CMOS circuit are realized. Furthermore this IPS scheme makes it possible to reduce the standby current of the SRAM to 0.4% compared with a conventional one at 100 MHz operation.