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A new scan architecture is proposed to reduce peak test power and capture power. Only a subset of scan flip-flops is activated to shift test data or capture test responses in any clock cycle. This can effectively reduce the capture test power and peak test power. Two routing-driven schemes are proposed to reduce the routing overhead. Experimental results show that the proposed scan architecture can effectively reduce peak test power, capture power, test data volume, and test application cost.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on (Volume:28 , Issue: 7 )
Date of Publication: July 2009