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Multi- {\rm J}_{\rm c} (Josephson Critical Current Density) Process for Superconductor Integrated Circuits

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3 Author(s)
Yohannes, D.T. ; HYPRES, Inc., Elmsford, NY, USA ; Inamdar, A. ; Tolpygo, S.K.

Many applications of superconductor integrated circuits may require a small part of the circuit to work at the highest possible clock frequency, e.g. an ADC in the receiver front-end, while more complex parts of the circuits may work at a lower frequency, e.g. a digital filter. Since the maximum clock frequency is proportional to the square root of the Josephson critical current density (Jc), such circuits can be realized as multi-Jc circuits containing trilayers with different Jc's. A fabrication technology will be presented enabling a single chip to accommodate circuits optimized for different critical current densities. Details of the multi-Jc process will be discussed as well as the typical circuit implementations and test results.

Published in:

Applied Superconductivity, IEEE Transactions on  (Volume:19 ,  Issue: 3 )