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This paper presents energy-efficient packet interface architecture and a power management technique for gigabit Ethernet controllers, where low-latency and high-bandwidth are required to meet the pressing demands of very high frame-rate data. More specifically, a predictive-flow-queue (PFQ)-based packet interface architecture is presented, which adjusts the operating frequency of different functional blocks at a fine granularity so as to minimize the total system energy dissipation while attaining performance goals. A key feature of the proposed architecture is the implementation of a runtime workload prediction method for the network traffic along with a continuous frequency adjustment mechanism, which enables one to eliminate the latency and energy penalties associated with discrete power mode transitions. Furthermore, a stochastic modeling framework based on Markovian decision processes and queuing models is employed, which make it possible to adopt a precise mathematical programming formulation for the energy optimization under performance constraints. Experimental results with a designed 65-nm Gb Ethernet controller show that the proposed interface architecture and continuous frequency scaling result in system-wide energy savings while meeting performance specifications.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:17 , Issue: 8 )
Date of Publication: Aug. 2009