Referenced Items are not available for this document.
The impact of high-order integrator dynamics on switched-capacitor sigma-delta modulator (????M) performances is investigated in this paper. An advanced generic integrator-settling model to take into account high-order dynamic effects is presented and validated by means of transistor-level simulations of circuits implemented in a commercial 0.35 ??m CMOS technology. The model is used through the paper to carry out an exhaustive behavioral analysis for second-order single-bit ????Ms characterized by first-, second-, and third-order integrator dynamics, showing how high-order poles and zeros can affect the ????M characteristics remarkably. The proposed analysis provides useful guidelines to fix a convenient integrator poles/zeros placement in order to achieve an effective ????M design flow.
Published in:
Circuits and Systems I: Regular Papers, IEEE Transactions on
(Volume:57
,
Issue:
3
)
Date of Publication: March 2010
- Page(s):
- 618 - 630
- ISSN :
- 1549-8328
- INSPEC Accession Number:
- 11156358
- Digital Object Identifier :
- 10.1109/TCSI.2009.2023946
- Product Type:
- Journals & Magazines
- Date of Publication :
- 02 June 2009
- Date of Current Version :
- 04 March 2010
- Issue Date :
- March 2010
- Sponsored by :
- IEEE Circuits and Systems Society
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