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Design of Power-Efficient Configurable Booth Multiplier

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2 Author(s)
Shiann-Rong Kuang ; Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan ; Jiun-Ping Wang

In this paper, a power-efficient 16times 16 configurable Booth multiplier (CBM) that supports single 16-b, single 8-b, or twin parallel 8-b multiplication operations is proposed. To efficiently reduce power consumption, a novel dynamic-range detector is developed to dynamically detect the effective dynamic ranges of two input operands. The detection result is used to not only pick the operand with smaller dynamic range for Booth encoding to increase the probability of partial products becoming zero but also deactivate the redundant switching activities in ineffective ranges as much as possible. Moreover, the output product of the proposed multiplier can be truncated to further decrease power consumption by sacrificing a bit of output precision. To efficiently and correctly combine these techniques, some additional components, including a correcting-vector generator, an adjustor, a sign-bit generator, a modified error compensation circuit, etc., are also developed. Finally, three real-life applications are adopted to evaluate the power efficiency and error performance of the proposed multiplier. The results show that the proposed multiplier is more complex than non-CBMs, but significant power and energy savings can be achieved. Furthermore, the proposed multiplier maintains an acceptable output quality for these applications when truncation is performed.

Published in:

IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:57 ,  Issue: 3 )