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Design and Implementation of a GALS Adapter for ANoC Based Architectures

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3 Author(s)
Thonnart, Y. ; LETI - MINATEC, CEA, Grenoble ; Beigne, E. ; Vivet, P.

As Globally Asynchronous Locally Synchronous (GALS) systems are becoming preponderant in complex SoC and NoC, we present the design and implementation of a new GALS adapter to be used in ANoC, an asynchronous NoC architecture. The proposed GALS adapter is a complete IP integration module, including a new FIFO based design using a Johnson-encoding principle for timing domains interfacing, and a local programmable clock generator for the IP unit. The GALS adapter has been implemented in a ST 65 nm technology in standard-cell based design. It is provided as a hard-macro for easy IP integration, can generate 256 clock frequencies from 25 MHz to 1 GHz, and achieves 500 MHz nominal throughput from a clocked domain to a QDI asynchronous logic NoC.

Published in:

Asynchronous Circuits and Systems, 2009. ASYNC '09. 15th IEEE Symposium on

Date of Conference:

17-20 May 2009