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Neural networks implementation with VLSI

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4 Author(s)
Georges, E.M. ; City Univ., London, UK ; Lai, L.L. ; Ndeh-Che, F. ; Braun, H.

This paper presents the design of a new and efficient winner-take-all (WTA) cell for the self-organising mapping (SOM) neuron. This cell is implemented in VLSI that provides both faster operation and a reduction in the number of transistors per cell compared to existing designs. The operation of the circuit is described and results of SPICE simulations are presented

Published in:

Artificial Neural Networks, 1995., Fourth International Conference on

Date of Conference:

26-28 Jun 1995