By Topic

Active corner engineering in the process integration for shallow trench isolation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Balasubramanian, N. ; Deep Submicron Integrated Circuits Department, Institute of Microelectronics, Singapore 117685 ; Johnson, E. ; Peidous, I.V. ; Ming-Jr, Shiu
more authors

Your organization might have access to this article on the publisher's site. To check, click on this link: 

The electrical characteristics of metal–oxide–semiconductor field effect transistor devices with shallow trench isolation (STI) have been studied to evaluate the active corner shaping and the trench-fill dielectric densification techniques. The suppression of corner parasitic transistor effects was observed in the two different corner shaping schemes used. In the first approach, an undercut of pad oxide below the nitride mask defining the active region facilitated corner oxidation during liner oxide growth. In the second approach, a high temperature post-chemical mechanical polishing (CMP) oxidation created a rounded corner, forming a minibird’s beak under the nitride mask edge. Cross-sectional transmission electron microscopy shows that, while the post-CMP oxidation “rounds” the corner, the pad oxide undercut produces a concave corner profile. Though both approaches improved the subthreshold characteristics of the transistor, the leakage current of field-edge-intensive diodes became very high for post-CMP oxidation. The leakage was also strongly influenced by the annealing ambient during densification of STI gap-fill dielectric. An oxidizing ambient resulted in high leakage current whereas a nonoxidizing ambient resulted in low levels of leakage current. The excessive leakage is attributed to the silicon defects generated along the STI edge as a result of stress exerted by the gap-fill oxide. Densification in nonoxidizing ambient also helped improve the subthreshold characteristics of the transistors with STI fabricated using the pad oxide undercut scheme. © 2000 American Vacuum Society.

Published in:

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures  (Volume:18 ,  Issue: 2 )