Referenced Items are not available for this document.
A novel architecture for an HDTV level MPEG2 decoder is developed, which consists of specific functional macrocells and macroblock level pipeline buffers. Owing to the sophisticated I/O interface among macrocells, macroblock level pipeline buffers are successfully incorporated with functional macrocells. A new organization of frame memory and interface is also devised. The designed decoder contains 454 K transistors, and occupies 81.0 mm2 with a 0.6 μm triple-metal CMOS technology
Published in:
Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on
Date of Conference: 6-10 Nov 1995
- Page(s):
- 468 - 471
- Meeting Date :
- 06 Nov 1995-10 Nov 1995
- Print ISBN:
- 0-7803-2624-5
- INSPEC Accession Number:
- 5262684
- Digital Object Identifier :
- 10.1109/TENCON.1995.496442
- Product Type:
- Conference Publications
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