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Synchronous test generation model for asynchronous circuits

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3 Author(s)
S. Banerjee ; Eng. Res. Center, AT&T Bell Labs., Princeton, NJ, USA ; S. T. Chakradhar ; R. K. Roy

Tests generated for asynchronous circuits using existing methods can be invalidated if the delay dependent nature and unstable states of the circuit are not considered during test generation. Test invalidation may result in a decrease in fault coverage. In this paper, we present a new method for testing asynchronous circuits. We propose a new synchronous test model (STM) that captures the essential behavior of the circuit under test. The STM has three advantages: (1) synchronous, sequential test generation techniques can be used to generate tests for the model, (2) tests generated for the STM can always be translated into tests for the circuit under test, and (3) these tests will not suffer from test invalidation due to unstable states, because the STM implicitly enforces the fundamental mode of operation during test generation. Experimental results on several benchmark show that our method generates test sets with high fault coverage and with absolutely no test invalidation. Several applications of the STM are also discussed

Published in:

VLSI Design, 1996. Proceedings., Ninth International Conference on

Date of Conference:

3-6 Jan 1996