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CMOS gate array implementation of SPARC

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2 Author(s)
Quach, L. ; Fujitsu Microelectron. Inc., Tokyo, Japan ; Chueh, R.

A description is given of the implementation of the 32-bit RISC (reduced-instruction-set-computer)-based SPARC (Scalable Processor Architecture) microprocessor chip set MB86900 and MB86910 using a CMOS 20K gate array to meet a tight development schedule while achieving high performance with high degree of testability. MB86900 is the CPU and MB86910 is the floating-point controller. Although these components were implemented in a gate array, the performance exceeds that of most of the existing commercial full-custom microprocessors.<>

Published in:

Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers

Date of Conference:

Feb. 29 1998-March 3 1988