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Modeling and Analysis of High-Speed I/O Links

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6 Author(s)
Balamurugan, G. ; Microprocessor Technol. Labs., Intel Corp., Hillsboro, OR ; Casper, B. ; Jaussi, J.E. ; Mansuri, M.
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Improvements in signaling methods, circuits and process technology have allowed input/output (I/O) data rates to scale beyond 10 Gb/s over several legacy channels. In this regime, it is critical to accurately model and comprehend channel/circuit nonidealities in order to co-optimize the link architecture, circuits, and interconnect. Empirical and worst-case analysis methods used at lower rates are inadequate to account for several deterministic and random noise sources present in I/O links today. In this paper, we review models and methods for statistical signaling analysis of high-speed links, and also propose a new way to integrate behavioral modeling approaches with analytical methods. A computationally efficient segment-based analysis method is shown to accurately capture the effect of transmit jitter and its interaction with the channel. In addition, a new jitter interpretation approach is proposed to enable the analysis of arbitrary I/O clocking topologies. We also present some examples to illustrate the practical utility of these analysis methods in the realm of high-speed I/O design.

Published in:

Advanced Packaging, IEEE Transactions on  (Volume:32 ,  Issue: 2 )

Date of Publication:

May 2009

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