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For more than two decades following the publication of the MOSFET scaling theory, CMOS engineers focused their efforts on scaling down the physical size of CMOS transistors. The opportunity for scaled CMOS to break into high-end applications came when the industry worked together to established voltage standards below 5 volt. Two of the limits of CMOS scaling were reached in the early 2000's: high tunneling current through the thin gate insulator and high device off current. Today, device engineers focus primarily on technology innovations for continued device performance improvement from one generation to the next.