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Browse Journals & Magazines > Electron Device Letters, IEEE ...> Volume:30 Issue:3 Help

Erase and Retention Improvements in Charge Trap Flash Through Engineered Charge Storage Layer

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10 Author(s)
Goel, N. ; FEP Group at SEMATECH, Austin, TX ; Gilmer, D.C. ; Park, H. ; Diaz, V.
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The simultaneous improvement in the erase and retention characteristics in a TANOS (TaN-Al2O3-Si3N4-SiO2-Si) flash memory transistor by utilizing the band-engineered and compositionally graded SiNx trap layer is demonstrated. With the process optimizations, a > 4V memory window and excellent 150 degC 24-h retention (0.1-0.5 V charge loss) for a programmed DeltaVt = 4V with respect to the initial state are obtained. The band-engineered SiNx charge storage layer enables flash scaling beyond the floating-gate technology with a promise for improved erase speed, retention, lower supply voltages, and multilevel cell applications.

Published in:
Electron Device Letters, IEEE  (Volume:30 ,  Issue: 3 )

Date of Publication: March 2009

Page(s):
216 - 218
ISSN :
0741-3106
INSPEC Accession Number:
10499184
Digital Object Identifier :
10.1109/LED.2009.2012397
Product Type:
Journals & Magazines
Date of Publication :
10 February 2009
Date of Current Version :
24 February 2009
Issue Date :
March 2009
Sponsored by :
IEEE Electron Devices Society

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