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The technique of wafer level chip scale package (WLCSP) is similar as flip chip packages without using underfill. The weakest point is solder joint reliability issue so the package size of WLCSP in current industry is used less than 10times10 mm2. In this paper, we use 5.5times5.5 mm2 package size to take as test vehicle and focus on ball peeling and shear stresses to assume and simulate drop test and thermal cycling conditions. In this paper, several parameters including die size, re-distribution layer (RDL), polyimide (PI) material and thickness, under-bump metallization (UBM) structure and PI opening factors are discussed and taken as optimal design guidelines. Then, in order to verify simulation accuracy, we use 1500 G peak acceleration and 1.0 ms pulse duration time in board level drop test and consider thermal loading interval from 125degC to -40degC in JEDEC thermal cycling test (TCT) to analyze design factor influence compared to simulation trend chart. In the conclusion of this paper, focus on ball shear stress analysis, the obvious factors are RDL, UBM structure and PI opening and minor factors are die size, PI material and thickness. WLCSP with RDL can reduce 41 % shear stress than without one. The thicker UBM and smaller PI opening (210 um -> 70 um) can reduce 26% and 24% shear stress, respectively. However, focus on ball peeling stress analysis, the obvious factors are RDL, UBM structure and PI thickness and minor factors are die size, PI material and opening. WLCSP with RDL can reduce 22% peeling stress than without one. The thinner UBM and thicker PI (5 um -> 10 um) can reduce 23% and 24% peelng stress, respectively.
Date of Conference: 1-2 Dec. 2008