A low offset rail-to-rail 12b 2MS/s 0.18μm CMOS cyclic ADC

A 12b 2 MS/s cyclic ADC achieves low power consumption with a single-ended rail-to-rail input signal range of 3.3 Vp-p. The proposed voltage reference scheme directly employing power supply voltages implements an offset voltage less than 1 mV without well-known calibration and trimming techniques. The prototype ADC in a 0.18 mum CMOS technology demonstrates the effective number of bits of 11.48 for a 100 kHz full-scale input at 2 MS/s. The ADC with an active die area of 0.12 mm
²
consumes 3.6 mW at 2 MS/s and 3.3 V(analog)/1.8 V (digital).