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2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology

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11 Author(s)
Dinesh Somasekhar ; Circuit Res. Labs., Intel Corp., Hillsboro, OR ; Yibin Ye ; Paolo Aseron ; Shih-Lien Lu
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We present 2 Mb 2T PMOS gain cell macro on 65 nm logic process that has high bandwidth of 128 GBytes/sec, fast cycle time of 2 ns and 6-clock cycles access time at 2 GHz. Macro features a full-rate pipelined architecture, ground precharge bitline, non-destructive read-out, partial write support and 128-row refresh to tolerate short refresh time. Cell is 2X denser than SRAM and is voltage compatible with logic.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:44 ,  Issue: 1 )