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An integer linear programming (ILP) model for mapping applications on HW platforms that consist of muPs, ASICs and FPGAs is proposed. The introduced model solves the assignment and scheduling problems taking into consideration the time required to reconfigure the FPGAs. Specifically, the type of the tasks that are executed on the FPGAs is taken into account, so that tasks which perform the same function are scheduled consecutively. In that way the number of the FPGAs' reconfigurations is reduced and the performance is improved. Also, the configuration of the FPGAs is hidden because it happens, if it is possible, in the time intervals that the FPGAs are idle. Thus, the execution time of the task mapped on the FPGA does not increase due to reconfiguration time and performance is improved. Moreover, the memory requirements for storing the program and configuration codes of the tasks that are executed on muPs and FPGAs are taken into consideration. In addition, resource conflicts due to tasks/data transfers whose execution times are overlapped in time and are assigned on the same resource (PE/bus) are addressed. Finally, resource sharing is supported. The above features are validated by a series of experiments including a real-application example, the M-JPEG encoder. Also, the complexity of the model is studied in terms of the number of the generated constraints and variables and time required for solving it.
Date of Publication: January 2009