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Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator

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2 Author(s)
Stefania Perri ; Dept. of Electron., Univ. of Calabria, Rende ; Pasquale Corsonello

This paper presents a new efficient architecture for the design of fast low-cost single-clock-cycle binary comparators. The proposed 64-bit circuit requires only 1051 transistors and, when implemented by using the ST 90-nm 1-V CMOS technology, it exhibits a running frequency higher than 4 GHz with an average power dissipation of only ~ 4 mW. Comparison with the fastest comparator known in the literature demonstrates that, at a parity of technology used, the novel architecture is ~ 12% faster and requires ~ 69% less transistors.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:55 ,  Issue: 12 )