Skip to Main Content
In this paper, the fast one-dimensional (1-D) algorithms and their hardware-sharing designs for the 1-D 2times2, 4times4, and 8times8 inverse transforms of H.264/AVC and the 1-D 8times8 inverse transform of AVS are proposed with the low hardware cost, especially for the multiple decoding applications in China. By sharing the hardware, the proposed 1-D hardware sharing architecture is realized by adding the offset computations, and it is implemented with the pipelined architecture. Thus, the hardware cost of the proposed sharing architecture is smaller than that of the individual and separate designs. With regular modularity, the proposed sharing architecture is suitable to achieve H.264/AVC and AVS signal processing by VLSI implementations.
Circuits and Systems II: Express Briefs, IEEE Transactions on (Volume:55 , Issue: 12 )
Date of Publication: Dec. 2008