Referenced Items are not available for this document.
A new dual-loop digital phase-locked loop (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high-frequency delta-sigma dithering to achieve wide PLL bandwidth and low jitter at the same time. The STDC exploits the stochastic properties of a set of latches to achieve high resolution. A prototype DPLL test chip has been fabricated in a 0.13-mum CMOS process, features a 0.7-1.7-GHz oscillator tuning range and a 6.9-ps rms jitter, and consumes 17 mW under 1.2-V supply while operating at 1.2 GHz.
Published in:
Circuits and Systems I: Regular Papers, IEEE Transactions on
(Volume:56
,
Issue:
8
)
Date of Publication: Aug. 2009
- Page(s):
- 1612 - 1621
- ISSN :
- 1549-8328
- INSPEC Accession Number:
- 10890332
- Digital Object Identifier :
- 10.1109/TCSI.2008.2010109
- Product Type:
- Journals & Magazines
- Date of Publication :
- 02 December 2008
- Date of Current Version :
- 28 August 2009
- Issue Date :
- Aug. 2009
- Sponsored by :
- IEEE Circuits and Systems Society
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