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Voltage-dependent timing skews in precharge and sensing activities cause functional failure and reduce the speed of asynchronous static random-access memory (SRAM). Data-dependent bitline-leakage current further increases the timing skews and reduces the yield of asynchronous SRAM. A dual-mode self-timed (DMST) technique is developed for asynchronous SRAM to eliminate the timing-skew-induced failures and speed overhead across various process, voltage, and temperature conditions. The DMST technique employs a single replica column and new dummy cells to track both precharge and sensing activities in asynchronous SRAM, with bitline leakage considered. The DMST-technique simulation uses both 65-nm and 0.35-mum technologies. Several 0.35-mum DMST SRAM macros were fabricated in a test chip and embedded in a mass-produced system-on-a-chip suitable for various battery/supply-voltage configurations. Measurements demonstrated that the DMST technique can be operated continuously over a wide range of supply voltages, from 39.4% to 151.5% (or 212.1%, given device durability) of the nominal supply voltage (3.3 V). The fabricated macros also confirmed that the DMST technique is scalable for various bitline lengths and offers the same area overhead as conventional sense-tracking-only replica-column schemes.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Volume:56 , Issue: 8 )
Date of Publication: Aug. 2009