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A variable-phase ring oscillator (VPRO) and phase-locked loop (PLL) architecture is introduced for integrated phased arrays. The architecture eliminates key building blocks such as mixers, phase shifters and power splitters/combiners, allowing for compact and low-power implementations. This paper presents the principles of operation of the architecture in transmit and receive modes, along with a detailed theoretical treatment of critical performance metrics such as linearity and sensitivity. In addition, measured results from a prototype, 24 GHz , 4-channel, phased-array transceiver, implemented in a 0.13 mum CMOS process, are presented.