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Conventional memory address decoders based on static CMOS gates incur high clock loading and unnecessary power dissipation in unselected banks. This paper presents a dynamic word line decoder which is fast, has reduced active and leakage power dissipation, and also enables faster race-free sense timing. In a multi-bank memory array with sixteen decoders, the energy-delay product of the dynamic decoder is 66% lower than a low-power static version. The design leverages the predictability of dynamic circuits to provide significant decoder leakage reduction in unselected banks. The dynamic decoder has been fabricated on a 90 nm bulk CMOS process. The measured test chip address to word line delay is 170 ps at 1.5 V and the measured leakage reduction is over 20x at V DD greater than 0.8 V.
Date of Publication: Nov. 2008