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A 430 MHz, 280 mW Processor for the Conversion of Cartesian to Polar Coordinates in 0.25 \mu\hbox {m} CMOS

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3 Author(s)
Strollo, A. ; Dept. of Electron. & Telecommun. Eng., Napoli Univ., Naples ; De Caro, D. ; Petra, N.

A novel architecture to realize the conversion of rectangular to polar coordinates is presented in this paper. The proposed technique for phase calculation uses a logarithmic number system and does not require any multiplications, but only a few small tables and a few multi-operand additions. The modulus is computed by a constant multiplier, a lookup table, and a full multiplier. A test chip has been designed and fabricated in 0.25 mum CMOS. The realized circuit uses a novel high-speed modified double-pass transistor (DPL) full-adder cell to improve performance. The test chip includes two processors. The first one computes only the phase and reaches 482 MHz maximum clock frequency, with 0.37 mW/MHz power dissipation. The second processor computes the phase and modulus and works up to 430 MHz, with 0.64 mW/MHz. The experimental results compare favorably with previously reported architectures.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:43 ,  Issue: 11 )

Date of Publication:

Nov. 2008

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