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Design of an All-Digital LVDS Driver

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4 Author(s)
Hungwen Lu ; Dept. of Electr. Eng., Nat. Central Univ., Jungli, Taiwan ; Hsin-Wen Wang ; Chauchin Su ; Liu, C.-N.J.

This paper presents an all-digital low-voltage-differential-signaling (LVDS) driver design for Serial Advanced Technology Attachment II. A simultaneous-switching-noise reduction technique and an autocalibration mechanism are implemented to suppress switching noise and to handle process and environmental variations. The circuit is implemented in a 0.18-mum 1P6M CMOS process with a core area of 0.072 mm2. At 3 Gbps, it consumes 9 mW of power under a 1.8-V power supply or 3 pJ/bit.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:56 ,  Issue: 8 )

Date of Publication:

Aug. 2009

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