By Topic

An 8 \times 8 Cell Analog Order-Statistic-Filter Array With Asynchronous Grayscale Morphology in 0.13- \mu{\hbox {m}} CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Jonne Poikonen ; Dept. of Inf. Technol., Univ. of Turku, Turku, Finland ; Ari Paasio

This paper presents an integrated 8 times 8 cell image processor array demonstrating the parallel implementation of analog order-statistic filtering and grayscale mathematical morphology. Each cell, connected locally to four nearest neighbors and sized 30 times 28 mum2, includes a digitally programmable five-input analog current-mode ranked-order filter. The array also demonstrates an implementation of asynchronously propagating morphological grayscale reconstruction, which is robust against device mismatch. The measurement results of all programmable order-statistic operations are shown, verifying the correct operation of the array. The chip was manufactured in a 0.13- mum 1-poly 6-metal CMOS technology and operates from a single 1.3-V power supply.

Published in:

IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:56 ,  Issue: 8 )