By Topic

Pipeline Architectures for Radix-2 New Mersenne Number Transform

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Nibouche, O. ; Sch. of Electr., Electron. & Comput. Eng., Newcastle Univ., Newcastle upon Tyne, UK ; Boussakta, S. ; Darnell, M.

Number theoretic transforms which operate in rings or fields of integers and use modular arithmetic operations can perform operations of convolution and correlation very efficiently and without round-off errors; thus, they are well matched to the implementation of digital filters. One such transform is the new Mersenne number transform, which relaxes the rigid relationship between the length of the transform and the wordlength in Fermat and Mersenne number transforms where the kernel is usually equal to a power of two. In this paper, three novel pipeline architectures that implement this transform are presented. The proposed architectures are scalable, parameterized, and can be easily pipelined; they are thus ideally suited to very high speed integrated circuit hardware-description-language (VHDL) descriptions. These architectures process data sequentially and have either one or two inputs and two or four outputs. The different input and output formats have resulted in the proposed architectures having different performances in terms of processing time and area requirements. Furthermore, they give the designer more choices in meeting the requirements of the application being implemented. A field-programmable gate array (FPGA) implementation of the proposed architectures has demonstrated that a throughput rate of up to 6.09 Gbit/s can be achieved for a 1024-sample transform, with samples coded to 31 bits.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:56 ,  Issue: 8 )