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Current testability analysis of feedback bridging faults in CMOS circuits

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2 Author(s)
Roca, M. ; Dept. of Phys., Univ. Illes Balears, Palma de Mallorca, Spain ; Rubio, A.

An exhaustive classification of bridging faults between pairs of logic level circuit nodes and an IDDQ testability analysis scheme for these faults are presented in this paper. The case of feedback bridging faults producing oscillations is considered in detail. The testability of such faults is verified through a set of experiments with specially implemented ASIC's

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:14 ,  Issue: 10 )

Date of Publication:

Oct 1995

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