By Topic

A single chip for optimal edge detection

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Zarka, N. ; Sci. Studies & Res. Centre, Syria ; Akil, M.

We present the architecture of a single chip for optimal edge detection of blurred and noisy 2D images. The chip has a systolic architecture which processes, in real time, any second order recursive filters. The chip is designed in 1.5 μ CMOS technology using COMPASS CAD tools. The chip area is 66.5 mm2, the number of transistors is about 182000 and the power consumption is 750 mW. This chip can be used in medical image edge detection

Published in:

Image Processing and its Applications, 1995., Fifth International Conference on

Date of Conference:

4-6 Jul 1995