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A single chip for optimal edge detection

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2 Author(s)
N. Zarka ; Sci. Studies & Res. Centre, Syria ; M. Akil

We present the architecture of a single chip for optimal edge detection of blurred and noisy 2D images. The chip has a systolic architecture which processes, in real time, any second order recursive filters. The chip is designed in 1.5 μ CMOS technology using COMPASS CAD tools. The chip area is 66.5 mm2, the number of transistors is about 182000 and the power consumption is 750 mW. This chip can be used in medical image edge detection

Published in:

Image Processing and its Applications, 1995., Fifth International Conference on

Date of Conference:

4-6 Jul 1995