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We describe a technique to double the throughput of bit-serial computational networks, while retaining the many advantages associated with this architectural approach. In essence this technique relies on a 2-wire radix-4 representation of serial data: a step towards bit parallelism. As the cost of data storage associated with bit-serial architectures is not increased by this technique, it has a favourable effect on overall area-time product. Novel use of the well-known modified-Booth recoding multiplication algorithm results in further area savings. A set of functional building blocks and interfacing conventions is outlined, forming the basis of a cell library for use in a silicon compilation environment.