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RAPAC: a high-speed image-processing system

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8 Author(s)
Elphinstone, A.C. ; University of Sheffield, Department of Electronic & Electrical Engineering, Sheffield, UK ; Heron, A.P. ; Hobson, G.S. ; Houghton, A.
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The paper describes the design and operation of a real-time image processing system and outlines one of its application areas. The system consists of a dedicated hardware processor called RAPAC (a reconfigurable attached processor architecture for convolution) and a host computer which is used for algorithm development and RAPAC control. RAPAC uses hardware processor units and multiple image memories, in a software controlled architecture, to process 5 MHz streams of pixel data. This processing rate allows it to process a 256 ¿¿ 256 pixel image in 20 ms, one field time of a standard TV camera. The result is either a new 256 ¿¿ 256 pixel image generated from the old image or a reduced data set which describes attributes of features in the image. These attributes are used by the host computer to calculate a decision output concerning the content of the image.

Published in:

Computers and Digital Techniques, IEE Proceedings E  (Volume:134 ,  Issue: 1 )

Date of Publication:

January 1987

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