By Topic

A 0.4 ps-RMS-Jitter 1–3 GHz Ring-Oscillator PLL Using Phase-Noise Preamplification

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Zhiheng Cao ; Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX ; Yunchu Li ; Shouli Yan

This paper presents the design and experimental results of a 0.4 ps rms jitter (integrated from 3 kHz to 300 MHz offset at 2.5 GHz) 1-3 GHz tunable ring-oscillator PLL for integrated clock multiplier applications. A new loop filter structure based on a sample-reset phase-to-voltage converter and a Gm-C filter decouples reference spur performance from charge-pump current matching and loop filter leakage, while enables phase error preamplification to lower PLL in-band noise without reducing VCO analog tuning range or increasing loop filter capacitor size. The ring-oscillator VCO features programmability of phase noise and power consumption at a given frequency. The PLL is implemented in a digital 0.13 mum CMOS process using only 1.2 V devices, occupies 0.07 mm2 and consumes 23 mW excluding reference clock receiver for 2.5 GHz output at the lowest phase noise mode.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:43 ,  Issue: 9 )