By Topic

Warpage reduction of package-on-package (PoP) module by material selection & process optimization

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Peng Sun ; Hong Kong Applied Science & Technology Research Institute, ASTRI, 1st Floor, 2 Science Park East Avenue, Hong Kong Science Park, Shatin, New Territories, China ; Vincent Chi-Kuen Leung ; Bin Xie ; Vivian Wei Ma
more authors

The package technology has matured significantly over the past several years, shifting from conventional components and direct board level assembly to chip or package level system integration. Two major commonly used approaches are System-on-Chip (SoC) and System-in-Package (SiP). Package-on-Package (PoP) that integrates logic die in the bottom package and memory die in the top package into a single 3D package is one of the promising SiP solutions. The major advantage of PoP packaging is that the top and bottom packages, which are usually designed with FBGA and PBGA package formats, can be tested individually before they are assembled. The yield loss of the whole PoP module can be reduced significantly. However, due to the Coefficient of Thermal Expansion (CTE) mismatch and the stiffness mismatch exist among EMC, substrate and silicon chip, warpages on both top and bottom packages are often observed. Large warpage could cause solder joint open failure and substrate delamination, leading to the electrical connection failure of the assembled module. Theoretically, three approaches can be used to solve the warpage issue of two BGA packages contained in a PoP module: package design, material selection and process optimization. Developing a new package or changing the existing design usually involves many efforts and needs long cycle time, which can not meet the needs of competitive microelectronics industry. The material selection and process optimization are often adopted by industry to achieve the goal of shortening time to market. In this paper, Finite Element (FE) simulation is performed firstly. The CTE of epoxy molding compound (EMC) is found to make an important contribution to the warpage of PoP. The guideline for materials selection is proposed. Based on this guideline, one type of "Green" EMC is selected. Material properties of EMC including filler content, curing degree, CTE and Tg are characterized with thermo-gravimetric analysis (TGA), differential scanni- g calorimetry (DSC) and thermo-mechanical analysis (TMA) respectively. The effect of the material properties and the post mold curing (PMC) process on the warpage behavior of FBGA package is investigated. Shadow moire system is employed to characterize the warpage of the molded block and signal units.

Published in:

Electronic Packaging Technology & High Density Packaging, 2008. ICEPT-HDP 2008. International Conference on

Date of Conference:

28-31 July 2008