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In this paper, we present a novel methodology for fully characterizing back-end interconnect lines. The use of the proposed new hybrid resistive e-test and SEM imaging algorithm addresses several practical issues. First it overcomes the inaccuracy of back-end estimation based on full capacitive measurement due to neglecting sidewall slope. Depending on the sidewall slope, a significant error in the estimation of line width, line thickness, side line space, and ILD thickness can result. This impact is shown to increase as interconnect geometry scales down. Secondly, it accommodates the limited silicon area in test chips. Finally, in addition to systematic behavior, the methodology accurately estimates and re-produces random component to fully re-construct the behavior of the interconnects on actual Si.