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Three-dimensional stress engineering in FinFETs for mobility/on-current enhancement and gate current reduction

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7 Author(s)
Saitoh, M. ; Corp. R&D Center, Toshiba Corp., Yokohama ; Kaneko, A. ; Okano, K. ; Kinoshita, T.
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In this paper, the first systematic study of uniaxial stress effects on mobility (mu)/on-current (Ion) enhancement and gate current (Ig) reduction in FinFETs is described. We demonstrate for the first time that Ig of (110) side-surface pFinFETs is largely reduced by longitudinal compressive stress due to out-of-plane mass increase. (110) n/pFinFETs are superior to (100) FinFETs in terms of higher mu/Ion enhancement ratio by longitudinal strain and comparable/higher short-channel Idsat. Three-dimensional stress design in FinFETs including transverse and vertical stresses is proposed based on the understanding of stress effects beyond bulk piezoresistance.

Published in:

VLSI Technology, 2008 Symposium on

Date of Conference:

17-19 June 2008