Referenced Items are not available for this document.
At the 22 nm node, we estimate that superior electrostatics and reduced junction capacitance in FinFETs may provide a 13~23% reduction in delay relative to planar FETs. However, this benefit is offset by enhanced gate-to-source/drain capacitance (Cgs) in FinFETs. Here, we measure FinFET Cgs capacitance at 22 nm-like dimensions and determine that, with optimization, the FinFET capacitance penalty can be limited to <6%, resulting in an overall advantage of up to 17% over a planar technology.
Published in:
VLSI Technology, 2008 Symposium on
Date of Conference: 17-19 June 2008
- Page(s):
- 12 - 13
- E-ISBN :
- 978-1-4244-1803-9
- Print ISBN:
- 978-1-4244-1802-2
- INSPEC Accession Number:
- 10140338
- Conference Location :
- Honolulu, HI
- Digital Object Identifier :
- 10.1109/VLSIT.2008.4588544
- Product Type:
- Conference Publications
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