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FinFET performance advantage at 22nm: An AC perspective

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27 Author(s)
M. Guillorn ; IBM Research, IBM T.J. Watson Research Center, Yorktown Heights, NY, USA ; J. Chang ; A. Bryant ; N. Fuller
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At the 22 nm node, we estimate that superior electrostatics and reduced junction capacitance in FinFETs may provide a 13~23% reduction in delay relative to planar FETs. However, this benefit is offset by enhanced gate-to-source/drain capacitance (Cgs) in FinFETs. Here, we measure FinFET Cgs capacitance at 22 nm-like dimensions and determine that, with optimization, the FinFET capacitance penalty can be limited to <6%, resulting in an overall advantage of up to 17% over a planar technology.

Published in:

2008 Symposium on VLSI Technology

Date of Conference:

17-19 June 2008