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A Two-Level Load/Store Queue Based on Execution Locality

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7 Author(s)
Pericas, M. ; Univ. Politec. de Catalunya, Barcelona ; Cristal, A. ; Cazorla, F.J. ; Gonzalez, R.
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Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahlpsilas law, such designs will be increasingly limited by the remaining sequential components of applications. To overcome this limitation it is necessary to design processors with many lower-performance cores for TLP and some high-performance cores designed to execute sequential algorithms. Such cores will need to address the memory-wall by implementing kilo-instruction windows. Large window processors require large load/store queues that would be too slow if implemented using current CAM-based designs. This paper proposes an epoch-based load store queue (ELSQ), a new design based on execution locality. It is integrated into a large-window processor that has a fast, out-of-order core operating only on L1/L2 cache hits and N slower cores that process L2 misses and their dependent instructions. The large LSQ is coupled with the slow cores and is partitioned into N small and local LSQs, one per core. We evaluate ELSQ in a large-window environment, finding that it enables high performance at low power. By exploiting locality among loads and stores, ELSQ outperforms even an idealized central LSQ when implemented on top of a decoupled processor design.

Published in:

Computer Architecture, 2008. ISCA '08. 35th International Symposium on

Date of Conference:

21-25 June 2008

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