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A multiplying-DLL-based frequency synthesizer with a fully integrated loop capacitor employs an adaptive current-adjusting loop to generate a low-jitter clock. The nonidealities in the general impedance converter (GIC) which is used as the loop capacitor are thoroughly discussed. Additionally, the discrete-time model for the clock generator with adaptive current tuning is presented and the analysis of the loop stability is provided. The frequency synthesizer occupies an active area of 0.09 mm2 in a 0.18-mum CMOS technology and consumes 9 mW from a 1.8-V supply. The measured rms jitter is 3.5 ps for a 229.5-MHz output clock.