By Topic

The Design and Analysis of a Fully Integrated Multiplying DLL With Adaptive Current Tuning

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Keng-Jan Hsiao ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei ; Tai-Cheng Lee

A multiplying-DLL-based frequency synthesizer with a fully integrated loop capacitor employs an adaptive current-adjusting loop to generate a low-jitter clock. The nonidealities in the general impedance converter (GIC) which is used as the loop capacitor are thoroughly discussed. Additionally, the discrete-time model for the clock generator with adaptive current tuning is presented and the analysis of the loop stability is provided. The frequency synthesizer occupies an active area of 0.09 mm2 in a 0.18-mum CMOS technology and consumes 9 mW from a 1.8-V supply. The measured rms jitter is 3.5 ps for a 229.5-MHz output clock.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:43 ,  Issue: 6 )