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A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35- \mu m CMOS

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6 Author(s)
Bonfanti, A. ; Dipt. di Elettron. ed Inf., Politec. di Milano, Milan ; De Caro, D. ; Grasso, A.D. ; Pennisi, S.
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A wideband frequency synthesizer architecture is presented. The proposed topology employs a direct digital frequency synthesizer (DDFS) to control the output frequency of an offset-PLL. In this way, the synthesizer features a very fine frequency resolution, 24 Hz, as in delta-sigma fractional-N PLLs, but without being affected by the quantization-induced phase noise. This, in turn, allows enlarging the loop bandwidth. The frequency synthesizer is designed to be employed as a direct modulator for Bluetooth transmitter in a low-cost 0.35-mum CMOS technology. At 2.5GHz it achieves 1.8-MHz bandwidth, while the settling time within 30ppm for an 80-MHz step is 3 mus. The integrated phase noise gives less than 1 degree of rms phase error and the worst-case spur is 48dBc at 1 MHz, well below the specifications. Power dissipation is 120 mW for the PLL core, 50 mW for the DDFS plus DACs, and 19 mW for the GFSK modulator.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:43 ,  Issue: 6 )