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Development of 38nm Bit-Lines using Copper Damascene Process for 64-Giga bits NAND Flash

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13 Author(s)
Byungjoon Hwang ; Semicond. R&D Center, Samsung Electron. Co., Ltd., Yongin ; Namsu Lim ; Jang-Ho Park ; Sowi Jin
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In order to develop high density NAND flash device, the increased number of cell strings for 1 page buffer forces to form a long bit-line with low sheet resistance, as well as low parasitic capacitance between bit-lines. In this paper, we secured a copper damascene process to form 38 nm bit-lines with 76 nm pitch using SADP (self-aligned double patterning) process. The methods to minimize the sheet resistance and to suppress the parasitic capacitance were explained on NAND flash device with 38 nm node technology.

Published in:

Advanced Semiconductor Manufacturing Conference, 2008. ASMC 2008. IEEE/SEMI

Date of Conference:

5-7 May 2008