This paper describes a methodology to measure process windows in-line at level using voltage contrast inspection and special families of test structures. This methodology allows rapid turn-around of experiments designed to find the most robust and best centered process conditions. Each family of structures should be laid out with a single super-pitch so that a single wafer scan can be used for one or more process windows. Rule based binning based on die X and Y coordinates is then used to separate out the results for each instance of the process window family. Three examples from the contact module are presented to illustrate the methodology. Structures to the monitor contact size, contact to poly space and contact pitch process windows are discussed.
Published in:
Advanced Semiconductor Manufacturing Conference, 2008. ASMC 2008. IEEE/SEMI
Date of Conference: 5-7 May 2008