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In this work, a new synchronization scheme for mesochronous communication is proposed. This design has better metastability tolerance compared to state-of-the-art synchronizers. It has low latency and is only composed of standard digital components. This solution avoids the prevalent assumption, in many contemporary synchronizing techniques, of solving the metastability in half a clock cycle. The new design achieves latency as low as one clock cycle for a 500 MHz, system clock, under 0.18 micron TSMC technology. A proof of concept simulation is performed and a comprehensive design methodology is proposed.