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A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues

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14 Author(s)
Ishikura, S. ; Matsushita Electr. Ind. Co., Ltd., Kyoto ; Kurumada, M. ; Terano, T. ; Yamagami, Y.
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We propose a new 2-port SRAM with a single read bit line (SRBL) eight transistors (8 T) memory cell for a 45 nm system-on-a-chip (SoC). Access time tends to be slower as a fabrication is scaled down because of threshold voltage (Vt) random variations. A divided read bit line scheme with shared local amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous read and write (R/W) access at the same row by using DBSA with the SRBL-8T cell. A rise of the storage node causes misreading. A read end detecting replica circuit (RER) and a local read bit line dummy capacitance (LDC) are introduced to solve this issue. A 128 bit lines - 512 word lines 64 kb 2-port SRAM macro using these schemes was fabricated by a 45 nm bulk CMOS low-standby-power (LSTP) CMOS process technology [1]. The memory cell size is 0.597 mum2. This 2-port SRAM macro achieves 7 times faster access time without misreading.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:43 ,  Issue: 4 )