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This work describes a programmable 10- to 100-MS/s, low-power 10-bit two-step pipeline analog-digital converter (ADC) operating at a power supply from 0.5- to 1.2-V. MOS transistors with a low-threshold voltage are employed partially in the input sampling switches and differential pair of the SHA and MDAC for a proper signal swing margin at a 0.5-V supply. The integrated adjustable current reference optimizes the static and dynamic performance of amplifiers at 10-bit accuracy with a wide range of supply voltages. A signal-isolated layout improves the capacitor mismatch of the multiplying digital-to-analog converter, while a switched- bias power-reduction technique reduces the power dissipation of comparators in the flash ADCs. The prototype ADC in a 0.13-mum CMOS process demonstrates the measured differential nonlin- earity and integral nonlinearity within 0.35 and 0.49 least significant bits. The ADC, with an active die area of 0.98 mm2, shows a maximum signal-to-noise distortion ratio and spurious free dynamic range of 56.0 and 69.6 dB, respectively, and a power consumption of 19.2 mW at a nominal condition of 0.8 V and 60 MS/s.
Circuits and Systems II: Express Briefs, IEEE Transactions on (Volume:55 , Issue: 4 )
Date of Publication: April 2008