Cart (Loading....) | Create Account
Close category search window
 

Process Development of Void Free Underfilling for Flip-chip-on-board

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Ming Ying ; Seagate Singapore Int. Headquarters Pte Ltd., Singapore ; Tengh, A. ; Yew Choon Chia ; Mohtar, A.
more authors

Flip-chip-on-board technology has gained its acceptance rapidly in printed circuit board assembly as one of choices for electrically challenged, form factor sensitive and high interconnect density applications. Due to the significant mismatch in the coefficients of thermal expansion among the materials of silicon chip and motherboard, solder bumps are subject to large thermal induced stresses which may lead to solder bump reliability issue. Underfilling of the mounted bare die is necessary in order to maintain the integrity of solder bumps to address the reliability issue. A key requirement of flip chip underfilling is that it should be void-free. Air trapped beneath the die or around solder bumps will result in reliability problems and possibly early component failures. In the present study, several potential root causes for underfill void are investigated for printed circuit board assembly to minimize process defects. Flip chips with lead-free solder bumps are mounted on a high Tg FR-4 based printed circuit board with non-solder mask defined pads. Flux dipping and normal convection reflow are adopted for printed circuit board assembly. No-clean flux is selected in order to eliminate flux clean process and hence to improve mass production output. Capillary-flow flux-compatible underfill is then needle dispensed to the bare dies. After underfill curing process, scanning acoustic microscope is employed for non-destructive underfill void detection. It is found that there are two key factors of achieving underfill void-free, one is the underfill gap between the flip chip active surface and printed circuit board top surface, and the other one is the assembled board holding time before underfill process. Larger underfill gap can help the flow to overcome surface tensions of the die/underfill and solder mask/underfill interfaces and also increase the wavefront speed. Shorter assembled board holding time has less risk of underfill void because of less moisture absorbed. Fl- ux type affects solder bump solderability and collapse height, and eventually the underfill gap. The flux with normal reaction activity level is suitable for fine pitch die in terms of maintaining a certain solder bump standoff height. Optimization of underfilling patterns can help to eliminate underfill void, but it is inflexible because of the limitation of the clearance between die to adjacent components for printed circuit board assembly. It is found that anhydride-based underfill has higher capability to wash the flux residues than phenol-based underfill. Selection of anhydride-based and finer filler size underfill material can reduce the amount of the voids and achieve a homogeneous flow.

Published in:

Electronics Packaging Technology Conference, 2007. EPTC 2007. 9th

Date of Conference:

10-12 Dec. 2007

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.