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A novel binary phase-shift keying (BPSK) demodulator architecture is presented. The design employs a phase frequency detector based phase-locked loop allowing for robust performance compared to prior art. Two different circuit implementations for the novel demodulator architecture are proposed. Based on theoretical analysis, the maximum data rate of the demodulator is derived to be 1/8th of the carrier frequency. For experimental validation, a prototype was implemented for a 13.56-MHz BPSK demodulator in a 0.5-mum CMOS technology. The circuit occupies 1 mm2 chip area and consumes 3-mW power without any circuit optimization and can be further improved. Bit-error rate measurements have also been presented for a 20-kbs data rate.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Volume:55 , Issue: 6 )
Date of Publication: July 2008